1. Field of the Invention
The invention relates to a method for fabricating a multilayer wiring board on which a semiconductor device, passive element electronic parts, functional elements or the like are mounted, a multilayer wiring board, and an electronic device using the same.
2. Description of the Related Art
In these days, it is desired that the electronic parts such as a semiconductor device, resistor, capacitor or the like are miniaturized and slimmed, for realizing the light-weighting of electronic apparatus such as a digital still camera, a video camera, and a cellular phone. For example, as to the resistor and capacitor, a 0603 (0.6 mm×0.3 mm) microchip resistors are put to practical use. In addition, as to the semiconductor chip, a bare chip is directly installed on a substrate without using a semiconductor package. Furthermore, even when the semiconductor package is used, a CSP (Chip Scale Package) in which a size of the semiconductor package is approximately same as that of the semiconductor chip is often used.
In the current of such miniaturization and slimming of the device, as a rigid wiring board with multilayered wirings for mounting these elements, so-called “buildup substrate” in which a plurality of wiring layers are stacked on via insulating layers is used recently. However, even in the field of the buildup substrate, a limit of the micro wiring layout is already conceived, so that a method for fabricating a high density wiring board compared with the method using the buildup substrate is strongly desired.
Accordingly, a wiring tape for TAB (Tape Automated Bonding) (hereinafter, referred as “TAB tape”) is recently used as a substrate for mounting a semiconductor device. This TAB tape is fabricated by sticking a copper foil on a thin film composed of polyimide or the like, and forming a wiring pattern on this copper foil. By using the TAB tape, there are advantages in that the minute wiring layout can be realized, that the thickness of the substrate can be reduced since a thin film is used, and that an area and a volume required for incorporation of the semiconductor device into the electronic device can be reduced since the substrate can be used with bending.
On the other hand, a FPC (Flexible Printed Circuit) is also used as a substrate for mounting a semiconductor device. This FPC is fabricated by using a thin film such as polyimide similarly to the TAB tape, and the FPC is advantageous in that the manufacturing of the device with a wide width is possible. The segregation in characteristics of the TAB tape and the FPC is as follows. The TAB tape is used for small-sized electronic apparatuses requiring the high density wiring board while the FPC is used for medium size electronic apparatuses using the ordinary wiring board.
As a technique for forming the wiring in the TAB tape or the like, the subtractive process, in which a copper layer formed on one surface of a substrate film is masked with a photoresist (photosensitive resin), and a part not to be used as a wiring is etched (removed) by solution to provide a wiring pattern, has been generally used. For example, Japanese Patent Laid-Open No. 2004-319593 discloses such subtractive process.
Nowadays, a wiring width and a wiring interval between wiring conductors of the TAB tape using this subtractive process is narrowed to a width of about 20 μm and a pitch of about 40 μm in mass-production level, by improving the photochemical etching process of the copper foil and by application of a thinner copper foil. However, the improvement of the wiring width and the wiring interval between the wiring conductors of the TAB tape using the subtractive process almost reaches to the technical limit.
In addition, in the subtractive process, there is a basic problem in that the wiring width is reduced in accordance with the progress of the etching (side-etching phenomenon). The photoresist is exfoliated due to the reduction in the wiring width, and chemical dissolution of the copper foil begins from the exfoliated part, as a result, defectiveness of the wiring due to the breaking of wire occurs. In addition, the wiring interval is increased by the reduction in the wiring adversely, so that a required wiring width is hardly obtained. As the corrective action, a correction of the photomask is conducted with considering the decrease in the wiring width and the increase in the wiring interval. However, the wiring width and the wiring interval of an etched product should be measured many times to be fed back to the photomask preparation, thereby causing the complication of the manufacturing process and the obstacle for shortening the product delivery date.
On the other hand, in the buildup substrate, a catalyst such as palladium (Pd) is provided on an insulating substrate and chemical copper plate is applied thinly then an electrolytic copper plating of about 10 μm is applied thereon. Finally, the wiring pattern is formed by the photo chemical etching. Therefore, in the buildup substrate, the basic problems due to the subtractive process are also left similarly to the FPC and the TAB tape.
Against the background as explained above, a method for fabricating a micro wiring board with a wiring pitch of 40 μm or less by using an additive process is studied in place of the subtractive process. The additive process is classified into a semi-additive process using the electrolytic copper plating method and a full-additive process using the electroless copper plating method.
The full-additive process is a process comprising the steps of providing the Pd catalyst on an electric insulating substrate, forming a plating resist by the photo process, conducting the electroless copper plating on an opening of the plating resist, exfoliating the plating resist thereafter, and removing the Pd catalyst provided right under the plating resist to form the wiring pattern. The full-additive process is disclosed, for example, by Japanese Patent Laid-Open No. 10-22634 and Japanese Patent Laid-Open No. 5-152746. On the other hand, the semi-additive process is a process comprising the steps of providing an electroless copper plating thinly, and forming a thick copper plating by using the electrolytic copper plating, by which the plating can be thickened in a short time compared with the electroless copper plating, to form the wiring pattern.
However, according to the additive process such as the full-additive process and the semi-additive process, the electroless copper plating is conducted by using a high temperature and high alkaline plating solution containing a copper complex such as EDTA-Cu. The plating solution to be used is expensive, in addition, the crystallization speed is 1/10 or less of the ordinary electroplating. Namely, the crystallization speed of the plating is extremely low. Further, the plating resist film is exfoliated due to the high temperature and high alkaline electroless copper plating solution. Still further, in the TAB tape and the FPC using a polyimide as the electric insulating substrate, the electric insulating substrate itself is chemically dissolved and damaged due to the high temperature and high alkaline electroless copper plating solution.
Recently, a method for forming a backing conductive layer by evaporation or sputtering in place of the electroless copper plating is used, so as to solve the above problems. In this method, for example, a coating such as titanium (Ti) or chromium (Cr) is provided to have a thickness of around 100 Å on a surface of a polyimide film, and a copper film with a thickness of about 3 μm is further provided on the coated surface. In this method, there are advantages in that provision of catalyst such as PD for the electroless copper plating is not necessary, and that the electroless copper plating can be omitted.
FIGS. 9A to 9H show an example of a conventional method for fabricating a multilayer wiring board (double-sided wiring board) using the aforementioned technique.
At first, a back surface copper foil 3 is stuck by adhesive to a back surface of an electric insulating material 1 composed of polyimide. Generally, a thickness of the polyimide film is about 20 to 50 μm, and a thickness of the copper foil is 10 to 20 μm. Next, a surface conductive layer 2A is formed on another surface (front surface) of the electric insulating material 1 (FIG. 9A). This surface conductive layer 2A is formed as follows. Firstly, a diffusion laminar film of, for example, chromium metal is formed to have a thickness of about 100 Å by sputtering, and a copper film is similarly formed to have a thickness of about 1000 Å by a vapor phase method such as the sputtering, then another copper film is grown thereon to have a thickness of about 3 μm by chemical copper plating or electrolytic copper plating.
Next, a conductive layer hole 4 is formed on the surface conductive layer 2A by photochemical etching method (FIG. 9B). Then a via hole 5 is opened by means of excimer laser and CO2 laser or reactive plasma using gas containing CF4 or the like (FIG. 9C).
Further, a process for providing a palladium catalyst layer 6 to provide an inner wall of the via hole 5 with the conductivity is conducted (FIG. 9D). Then an electroplating copper layer 7 is formed thereon (FIG. 9E).
Next, a photosensitive etching resist is coated on the front surface then a photosensitive etching resist pattern 8 is formed by exposure and development (FIG. 9F). Then a surface wiring layer 9 is formed by using a chemical etching solution such as aqueous ferric chloride and the photosensitive etching resist is removed (FIG. 9B).
For the back surface copper foil 3, a back surface copper wiring layer 10 is similarly formed by the photochemical etching so that a double-sided wiring board 11 is completed (FIG. 9H). The above-mentioned method is actually applied, as one of the methods for forming a wiring on the buildup substrate.
However, there are following disadvantages in the conventional methods for forming a multilayer wiring board.
(1) Limit of the Wiring Density
Since the wiring layer is formed by the chemical etching (the subtractive process), an edge of the surface wiring layer 9 has a trapezoidal cross section due to the side etching, so that the wiring width and the wiring interval in the finished state are fluctuated from the design values of the wiring width and the wiring interval as shown in FIG. 9G. Therefore, it is necessary to correct the mask to be used for the exposure. In addition, since a degree of the side etching depends on the wiring density, the spray condition of the etching solution or the like, it is difficult to prevent the variation of the wiring width and the wiring interval even if the correction is conducted. Accordingly, as described above, when using the conventional chemical etching, the wiring interval of 40 μm is the limit for the mass production in the high density wiring board such as the TAB tape.
(2) Prolongation and Complication of the Manufacturing Process
The vapor phase method such as the sputtering is used for forming the surface conductive layer 2A, so that it takes a long time for the film formation. In addition, since the surface wiring layer 9 and the back surface wiring layer 10 are formed in separate processes as shown in FIGS. 9A to 9H, the manufacturing process becomes complicated.
(3) Expensive Process Equipment
Since the vapor phase method such as the sputtering is used for forming the surface conductive layer 2A, the equipment used for the process is very expensive.